This invention relates to semiconductor devices and, particularly, to semiconductor power devices of the MOS-gated type designed in view of avalanche breakdown considerations.
By "MOS-gated" type is meant semiconductor devices including a gate control structure comprising a gate electrode overlying, but dielectrically isolated from, a first surface of a semiconductor substrate including, at the surface, source and drain regions separated by a channel region. Operation of the devices is under control of voltages applied to the gate electrode for controlling the conductivity of a path for current through the channel region between the source and drain regions. While a number of different types of MOS-gated devices now exist, e.g., insulated gate bipolar transistors (IGBTs) and MOS controlled thyristors (MCTs), and while the present invention can be used in all such devices, the greatest utility of the invention is in "unipolar" devices, particularly, metal-oxide-semiconductor field-effect transistors (MOSFETs). In such unipolar devices, only one type of majority charge carriers (holes or electrons) is present, and the resistivity of the device semiconductor material is relevant to device performance. As described hereinafter, the invention enables higher conductivity devices.
Additionally, the invention has greatest utility in devices where the drain region extends to the substrate first surface for being disposed between oppositely disposed channel "regions" (which may be part of a common annular channel region), and where the drain region voltage is applied to the drain region at a position beneath the channel region(s). The portion of the drain region adjacent to the substrate first surface and between the oppositely disposed channel regions is referred to as the drain "neck".
Avalanche breakdown in semiconductor devices is well-known and occurs when charge carriers arriving at a reverse biased p-n junction are accelerated by the field in the junction depletion region and receive enough energy so that, in collisions with the substrate lattice, the charge carriers ionize electrons and holes which repeat the process and lead to large current flow across the otherwise reverse biased junction. The reversed biased junction of concern to the present invention is the p-n junction between the channel region and the drain region which must withstand the voltage difference between the device source and drain regions when the device is in its current non-conducting, voltage blocking (off) condition.
In general, higher avalanche breakdown capability is provided by the use of higher resistivity (lower doped) semiconductor materials adjoining the p-n junction. Typically, in devices of the type under consideration, such junctions are "abrupt" junctions, (e.g., p.sup.+ -n.sup.-), where substantially the entire voltage drop occurs across a high resistivity semiconductor region on the drain side of the p-n junction. A problem with this, however, is that the higher the resistivity of the semiconductor material, particularly in unipolar devices where the current density is generally not sufficiently high for "conductivity modulating" the resistivity of the material (in effect, negating it), the higher are the voltage drop across the device and the I.sup.2 R heating of the device. Preferably, such parameters should be as low as possible and the present invention is directed to this goal.